1. Field of the Invention
The invention relates to methods, systems, and program products for evaluating the behavior of designed circuit components, by, for example, transforming a high-level, multi-domain design into its hardware implementation.
2. Background Art
Gating logic is an essential part of systems with multiple chips or multiple clock domains. The purpose of gating logic is to prevent spurious logic activity from “contaminating” a domain under test while the system is in the process of being reset or reconfigured. That is, when an incoming fence signal is active on a particular chip or domain, the internal logic on the chip or domain must be impervious to random transitions that may be present on any number of incoming interface busses or signals.
Thus, a complete verification of gating logic requires demonstration that all logic associated with a particular fence or set of fences is effectively quiesced during any window of time that the fences are active. Since a single fence line typically serves to protect a multitude of interface signals from causing downstream logic activity to occur, simulation alone is typically not sufficient to provide coverage on every possible interface transition scenario. This is non-trivial since any design bugs in gating logic that are not found prior to design release can pose the disastrous possibility of rendering the hardware useless. Therefore, a more robust method of verifying gating logic is needed to provide enhanced problem discovery capability and coverage.